1. Field of the Invention
The present invention relates to digital data communication, processing, storage and retrieval. More specifically, the present invention relates to error detection and correction Systems for digital data communication, processing storage and retrieval systems.
While the present invention is described herein with reference to illustrative embodiments for particular applications, it should be understood that the invention is not limited thereto. Those having ordinary skill in the art and access to the teachings provided herein will recognize additional modifications, applications, and embodiments within the scope thereof and additional fields in which the present invention would be of significant utility.
2. Description of the Related Art
For certain applications, accurate communication, processing, storage and retrieval of digital data is critically important. For these applications, error detection and correction schemes are employed to detect and, in many cases correct, bit errors in the digital data.
Originally, data was stored in one bit modules in memory allowing for the use of Hamming codes for data error detection and correction. Hamming codes were relatively simple, using stored parity over certain bits to determine which bit, if any, was in error. As memories grew larger, data was more often stored in larger (e.g. four bit) modules to minimize parts count, power consumption, cost and other factors associated with the design, manufacture and operation of the data communication, processing, storage and/or retrieval system. Thus, instead of storing data in a memory one bit wide and 256 rows deep, memory might be stored four bits wide and 256 rows deep.
For the multiple bit module, new and more powerful data error detection and correction schemes were required over any or all bits of a single module. For this purpose, the Reed-Solomon codes were found particularly well suited for providing multi-bit correction up to the width of an entire module.
Unfortunately, for the demands of many current applications, Reed-Solomon codes have been found to be too slow. Accordingly, a need remains in the art for a faster error detection and correction system for multiple bit modules in digital data communication, processing, storage and retrieval systems.
The need in the art is addressed by the present invention which provides fin improved multi-bit error correction system. The inventive error correcting system performs a fast error correcting operation on individual bits within multi-bit modules. In a specific implementation, the invention uses a Hamming code and divides an n times m bit data word into n modules, with each module having m bits. Next, the ith bits of each module are combined to form a set of parity bits. Syndrome bits are generated from the parity bits and used to locate errors in the bits and provide an indication of same. Finally, errors in the bits are corrected in a conventional manner to provide corrected data bits.
The invention therefore provides high speed error detection and correction for multiple bit modules in digital data communication, processing, storage and retrieval systems.